Researchers at the University of Southern California (USC) have combined two of our favorite materials — carbon nanotubes and IGZO — to create a new hybrid computer chip design that is flexible, transparent, and more energy efficient than conventional silicon chips. Potential applications include flexible OLED displays, circuits, memory, and sensors, eventually leading towards flexible, wearable computers — which, as you may have noticed, appears to be the direction that the computing industry is moving towards.
Carbon nanotubes (CNTs), as we reported on last week, are creeping ever closer to becoming a viable replacement to silicon in field-effect transistors (FETs). Transistors fashioned out of CNTs are much smaller than their silicon counterparts, and thus could enable the reinstatement of Moore’s law. IGZO (indium, gallium, zinc oxide) is a mature semiconductor that’s used in modern thin-panel (LCD and OLED) displays. IGZO’s main advantage is that it’s transparent. CNTs are flexible and transparent, too.
Both materials are theoretically very powerful — but so far, while it’s been easy enough to make p-type CNT transistors and n-type IGZO transistors, the inverse (n-type CNT, p-type IGZO) has proven hard to crack, making it impossible to create a single chip out of CNTs or IGZO. Instead of trying to force the matter, Chongwu Zhou and colleagues at USC decided on an alternate approach: a hybrid circuit design that uses p-type CNT transistors and n-type IGZO transistors. ["Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors"]
IGZO/CNT hybrid circuit, under a micrograph (in this case, a 51-stage ring oscillator)
This novel hybridization works a bit like a metal alloy: The strengths of the two materials shine through, while their weaknesses are mitigated. In this case, the CNT-IGZO hybrid circuit reduces power loss and increases efficiency. When the transistors are built on a polymer substrate, the whole thing is flexible, too. So far, the researchers have managed to build a circuit consisting of 1,000 hybrid transistors — not bad, but obviously a long way to go. (That’s one of the main barriers to the deployment of new, non-silicon materials: Developing the tools and processes that can accurately and reliably create billions of transistors on a substrate the size of your fingernail.)
In terms of electrical characteristics, the hybrid chips appear to tick all the right boxes. Electron mobility, drain current, and on/off ratio all seem to be pretty good. The next step, as always, is for the USC researchers to build more complicated circuits using their hybrid integration approach, as well as improving fabrication on flexible substrates — which then leads into wearable computers and other similar applications.
Speaking to Kurzweil AI, one of the researchers said the technology “may become sufficiently mature and be commercialized in ten years” — which might sound like a long time, but in the world of nanoelectronics and oxide layer thicknesses measured in atoms, it’s fairly reasonable.
